Manufacturing method of semiconductor device

ABSTRACT

A method of manufacturing a low power dissipation semiconductor power device is provided which is easy to perform and suitable for mass production. When a first and second conductivity-type regions are formed on a semiconductor substrate which is selectively irradiated by impurity ions, an excellent super junction is formed by controlling the ion acceleration energy and the width of each irradiated region so that the first and second conductivity-type regions may have a uniform impurity distribution and a uniform width along the direction of irradiation. Another method of manufacturing a low power dissipation semiconductor power device having an excellent super junction is provided which selectively irradiates a collimated neutron beam onto a P +  silicon ingot and forms an N +  region that has a uniform impurity distribution and a uniform width along the direction of irradiation in the P +  silicon ingot.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 11-181687, filed Jun. 28,1999, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention generally relates to a method of manufacturingsemiconductor devices, and more particularly relates to a method ofmanufacturing low power dissipation semiconductor power devices.

Some of the low power dissipation semiconductor power devices of theprior art have a junction structure (hereafter referred to as “superjunction”) consisting of a vertical junction group where a firstconductivity-type region and a second conductivity-type region arealternatively arranged vertically to the surface of a silicon substrate.

There is a prior method of creating such super junction structure byrepeating N⁻ epitaxial growth and ion implantation. FIG. 1 provides abrief explanation of this manufacturing process. In FIG. 1, a flow ofthe manufacturing process is shown in the right-hand part and crosssections of the silicon substrate at each step in the left-hand part.

As shown in FIG. 1, an N⁺ silicon substrate 101 is prepared and on thatan N⁻ epitaxial layer 102 is grown. Then boron-ions are implanted by theuse of an ion implantation mask (not shown) to form P⁺ regions 103 inthe N⁻ epitaxial layer 102. Subsequently, by the use of an inverted maskof the ion implantation mask, phosphorous ions are implanted in a regionadjacent to the P⁺ regions 103 to form N⁺ regions 104.

These ion-implanted regions are activated by annealing (not shown) toprovide the P⁺ regions 103 and N⁺ regions 104. Annealing can beperformed either after each ion implantation or after all theimplantations have been completed. In this way, a PN junction plane isformed as part of a super junction consisting of PN junctions verticallyarranged to the surface of an epitaxial layer.

Next, another N⁻ epitaxial layer 102 is grown and, as shown in theright-hand part of FIG. 1, the steps from boron implantation to N⁻epitaxial growth are repeated. Then a vertical super junction is formedwhere PN-junction planes are alternatively created in the verticaldirection to the wafer surface.

The N⁺ silicon substrate 101, which was used at an early step, will be adrain region of the low power dissipation semiconductor power device.Since the manufacturing method to be employed in the processes after theformation of a super junction is described later in FIG. 6D, detailexplanation is not given here.

If a low power dissipation semiconductor power device having this superjunction structure is manufactured to which high voltages are applied,since drain junction planes are formed by P⁺ and N⁺ regions that extendvertically to the wafer surface and a current path is created in the N⁺layer in the inner bulk region of the silicon substrate, the low powerdissipation semiconductor power device of NMOS-type shows a low ONresistance and a high drain withstand voltage.

A shortcoming in the above prior art is that such manufacturing methodof repeating the epitaxial growth process to create low powerdissipation semiconductor power devices is costly, difficult toimplement and not suitable for mass production.

BRIEF SUMMARY OF THE INVENTION

The present invention has been made to solve the above problem and itsprincipal object is to provide a method of manufacturing low powerdissipation semiconductor power devices having the super junctionstructure.

The present invention employs not the low-yield epitaxial growth processbut a method suitable for mass production by irradiating particle beamssuch as an ion beam and a neutron beam onto semiconductor substrates toprovide low power dissipation semiconductor power devices having thesuper junction structure at low cost and with ease.

To be more specific, the present invention is a semiconductor devicemanufacturing method of forming a second conductivity-type region byirradiating impurity ions selectively onto a first conductivity-typesemiconductor substrate, wherein the above impurity ion irradiatedregion is restricted by a shield mask that intercepts the impurity ionsand the acceleration energy of impurity ions is controlled so that theimpurity concentration in the second conductivity-type region may beuniform along the direction of irradiation.

The present invention is a semiconductor device manufacturing method offorming at least one of a first conductivity-type region and a secondconductivity-type region in the semiconductor substrate by irradiatingimpurity ions selectively onto the semiconductor substrate, wherein theimpurity concentration is uniform along the direction of irradiation inthe first and second conductivity-type regions and the impurity ionacceleration energy and the area of irradiated region are controlled tomake the cross-sectional shape and the cross-section area of each of thefirst and second conductivity-type regions on planes vertical to theirradiation direction uniform along the direction of irradiation.

In a preferred embodiment of the present invention, the area ofirradiated region is controlled by an electric sweeping or magneticsweeping of the impurity ion beam, or by movement of the semiconductorsubstrate. In the control of the ion acceleration energy and the area ofthe irradiated region, the area of the irradiated region is changedaccording to changes in the ion acceleration energy.

Further, in another preferred embodiment of the present invention, thearea of the irradiated region is controlled with a shield maskintercepting the impurity ions, and the acceleration energy and the areaof the irradiated region are controlled by changing the aperture area ofthe mask according to changes in the acceleration energy.

The present invention is a semiconductor device manufacturing method offorming a first and second conductivity-type regions by irradiatingimpurity ions selectively onto a semiconductor substrate; wherein twoshielding masks in a reversed imaging relation to each other are used torestrict the impurity ion irradiated regions so that the cross-sectionalshape and the cross-section area of the first and secondconductivity-type regions on planes vertical to the irradiationdirection may be uniform in the direction of irradiation; and theimpurity ion acceleration energy is controlled to make the impurityconcentration in the first and second conductivity-type regions uniformin the direction of irradiation.

The present invention is a semiconductor device manufacturing method offorming an N⁺ region by selectively irradiating a neutron beam onto a P⁺semiconductor ingot, wherein the incident angle of the neutron beam iscollimated so that the cross-sectional shape and the cross-section areaof the N⁺ region may be uniform in the direction of irradiation and sothat the impurity concentration in the N⁺ region may be uniform in thedirection of irradiation.

In a preferred embodiment of the present invention, the P⁺ ingot is madeof one of silicon, germanium and silicon carbide, and the incident angleof the neutron beam is parallel to the direction of a growth axis of theP⁺ semiconductor ingot.

The foregoing and other objects, features and advantages of theinvention will become more readily apparent from the following detaileddescription of the present invention which proceeds with reference tothe accompanying drawings.

Additional objects and advantages of the invention will be set forth inthe description which follows, and in part will be obvious from thedescription, or may be learned by practice of the invention. The objectsand advantages of the invention may be realized and obtained by means ofthe instrumentalities and combinations particularly pointed outhereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

The accompanying drawings, which are incorporated in and constitute apart of the specification, illustrate presently preferred embodiments ofthe invention, and together with the general description given above andthe detailed description of the preferred embodiments given below, serveto explain the principles of the invention.

FIG. 1 shows a prior art method of forming a super junction;

FIG. 2A shows a boron distribution provided by a low energy ionirradiation according to a first embodiment of the present invention;

FIG. 2B shows a boron distribution in the horizontal direction providedby a low energy ion irradiation according to a first embodiment of thepresent invention;

FIG. 2C shows a boron distribution in the vertical direction provided bya low energy ion irradiation according to a first embodiment of thepresent invention;

FIG. 3A shows a boron distribution provided by a high energy ionirradiation according to a first embodiment of the present invention;

FIG. 3B shows a boron distribution in the horizontal direction providedby a high energy ion irradiation according to a first embodiment of thepresent invention;

FIG. 3C shows a boron distribution in the vertical direction provided bya high energy ion irradiation according to a first embodiment of thepresent invention;

FIG. 4A shows a method of forming a super junction by an ion irradiationaccording to a first embodiment of the present invention;

FIG. 4B shows a boron distribution in the horizontal direction in asuper junction provided by an ion irradiation according to a firstembodiment of the present invention;

FIG. 4C shows a boron distribution in the vertical direction in a superjunction provided by an ion irradiation according to a first embodimentof the present invention;

FIG. 5 shows a method of forming a super junction by the use of shieldmasks according to a second embodiment of the present invention;

FIGS. 6A-6D show a method of forming a super junction by the use ofreversed imaging shield masks according to a third embodiment of thepresent invention; and

FIG. 7 shows a method of forming a super junction by a neutron beamirradiation according to a forth embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Now referring in detail to the drawings, the embodiments of the presentinvention are explained. Referring to FIGS. 2A, 2B, 2C and FIGS. 3A, 3B,3C, and FIGS. 4A, 4B, 4C, an example of the method forming a superjunction by an ion implantation according to a first embodiment of theinvention is explained.

As shown in FIG. 2A, when a low energy boron-ion beam 2 is irradiatedonto an N⁺ silicon substrate 1, the implanted boron-ions lose energywithin a short projection range in the N⁺ silicon substrate 1 and thenform a boron stopped region 3 near the surface.

The boron distributions in a horizontal direction along the surface ofthe N⁺ silicon substrate 1 and in a vertical direction along itsthickness become like those shown in FIGS. 2B and 2C, where thehorizontal coordinate of the region irradiated by the ion beam 2 isshown along the X-axis, the vertical coordinate toward the bottom of theN⁺ silicon substrate along the Z-axis and the boron distribution alongthe Y-axis.

The region irradiated by a boron-ion beam is set to present a stripedshape that has a width W on the substrate surface and normal to the pagesurface. The irradiation of the boron beam is performed to electricallysweeping the beam in the vertical and horizontal directions on theirradiated region.

The sweeping can also be performed by a magnetic sweep and movement ofthe N⁺ silicon substrate 1.

The control of the boron beam irradiation can also be performed by usinga boron-ion beam which is broadened to a flux beam and a striped shapeshield mask which is inserted between the boron-ion source and thesilicon substrate, with the aperture width W of this shield mask beingvaried.

Since the projection range of the boron-ion beam 2, ranging from thesurface of the N⁺ silicon substrate, is short in the case of irradiationwith low energy, the cross-sectional shape of the boron stopped region3, which is parallel to planes vertical to the ion incident direction(planes parallel to the surface, if the irradiation is made normal tothe surface), becomes almost equal to the shape of the boron-ionirradiated region.

The distribution of boron in the N⁺ silicon substrate 1 is explained infurther detail. As shown in FIG. 2B, the boron distribution shows analmost flat profile along the horizontal direction over the boron-ionirradiated region, accompanied by lateral broadening at the both ends ofthe irradiated region.

Also as shown in FIG. 2C, a peak in boron concentration appears at ashallow position from the surface of the N⁺ silicon substrate 1, ofwhich depth is equal to the projection range of boron-ions. Theimplanted boron receives a heat treatment for activation in thesubsequent annealing step, and the boron stopped region 3 turns into aP⁺ region, as shown by a right-down crossbatch in FIG. 2A.

In FIGS. 3A, 3B, 3C and FIGS. 4A, 4B, 4C, a boron-ion beam of highenergy 2 is irradiated onto the surface of the N⁺ silicon substrate 1.As shown in FIG. 3A, since the projection range of the boron implantedinto the N⁺ silicon substrate 1 is long in the case of a high energyirradiation of boron-ion beam 2, a boron stopped region 3 can be formednear the back surface of the N⁺ silicon substrate 1. In FIGS. 3A, 3B, 3Cand 4A, 4B 4C, like numbers refer to like components as in FIGS. 2A, 2Band 2C.

As mentioned before, the boron distribution in the N⁺ silicon substrate1 has lateral broadening. In order to make the width W of the boronstopped region 3 formed near the back surface in FIG. 3A equal to thewidth W of the boron stopped region 3 of FIG. 2A, the width W′ of theboron irradiation region should be narrower than that of FIG. 2A (W′<W),as indicated by the dashed lines in FIG. 3A.

When a boron stopped region 3 is formed near the back surface of the N⁺silicon substrate 1 by a high energy irradiation, a peak in boronconcentration appears near the back surface, as shown in FIG. 3C. In theregions other than the boron stopped region 3 between the dashed linesin FIG. 3C, accelerated high energy boron-ions simply pass through andalmost no boron is doped there. Only the boron stopped region 3,therefore, turns into a P⁺ region, as shown by a right-down crossbatchin FIG. 3A, in the subsequent heat treatment for activation of implantedboron.

While a high energy irradiation, thus, can form a P⁺ region deep in theN⁺ silicon substrate 1, it cannot form a P⁺ region between the surfaceand the P⁺ boron stopped region 3, because boron is not doped there.

As shown in FIGS. 4A and 4C, in order to form a striped-shape P⁺ boronimplanted region 3a having a uniform width W extending from the surfaceof the N⁺ silicon substrate 1 through its back surface, the accelerationenergy of implanted boron-ions should be varied continuously to adjustthe projection range of boron-ions in the N⁺ silicon substrate 1 so thata uniform boron distribution may be obtained in the vertical direction.

Namely, since the lateral broadening becomes larger as the projectionrange becomes larger, the width W′ of the boron irradiated region iscontrolled to be smaller (W′<W) as the acceleration energy is higher andthe projection range is deeper, so that the boron concentration and thewidth W of the boron implanted region 3a may be uniform in a verticaldirection, as shown in FIG. 4A.

The boron projection range may be controlled by gradually increasing theacceleration energy to extend from the surface of the N⁺ siliconsubstrate 1 through its back surface or may be controlled by graduallydecreasing the acceleration energy to extend from its back surface tosurface. In the subsequent heat treatment for activation of implantedboron, the boron implanted region 3a turns into a P⁺ region, and then asuper junction can be formed across the N⁺ silicon substrate 1.

In the above first embodiment of the invention, the boron irradiatedregion has been formed to present a slit-like shape and its width W′ hasbeen controlled. The shape of the irradiated region, however, is notnecessary slit-like.

Whatever shape the irradiated area may present, by controlling theirradiated region according to the boron-ion acceleration energy, it ispossible to make the boron concentration in the P⁺ boron implantedregion 3a uniform along the direction of irradiation and make thecross-sectional shape and the cross-section area of the P⁺ boronimplanted area 3a on planes perpendicular to the direction ofirradiation uniform along the direction of irradiation.

In this way, any arbitrary shape can be taken as the cross-section ofthe P⁺ boron implanted region 3a, and thus the application range ofsuper junction to devices can be widened. This is also true for thefollowing embodiments of the invention.

Now referring to FIG. 5, a second embodiment is explained, where a superjunction is formed by a boron-ion implantation using a resist mask. InFIG. 5, what denoted as 1 is an N⁺ silicon substrate, 2 a boron-ionbeam, 3a a P⁺ boron implanted region and 4 a shield mask made of aphotoresist.

First, using a Photo Engraving Process (PEP), a shield mask 4intercepting boron-ion beam is formed which has opening portionsallowing boron-ion irradiation. Onto its opening portions, the boron-ionbeam 2 is irradiated with its acceleration energy being variedcontinuously. Then the boron-ion beam can be irradiated as a whole bythe use of a wide flux beam. The boron-ion beam can either be sweptelectrically or magnetically. Also the sweeping can be performed bymoving the N⁺ silicon substrate 1.

As described in the first embodiment, the boron projection range in theN⁺ silicon substrate 1 is controlled to provide a uniform concentrationof boron vertically in the P⁺ boron implanted region 3a. Then not onlythe acceleration energy but also the beam current can be controlled toadjust the dose amount.

The boron acceleration energy and its dose amount are controlled so thatthe boron-ion projection ranges may overlap each other to provide auniform boron distribution in the vertical direction in the N⁺ siliconsubstrate 1. Since the lateral broadening become larger by boronscattering as the projection range becomes deeper, the thickness of theN⁺ silicon substrate 1 should be chosen so that the striped-shape P⁺boron implanted regions 3a may not overlap each other near the backsurface of the substrate.

In the subsequent heat treatment for activation of implanted boron, theboron implanted region 3a, shown by a right-down hatch in FIG. 5, turnsinto a P⁺ region, and then a super junction is formed across the N⁺silicon substrate 1.

If an N⁺ region (corresponding to 101 in FIG. 1), which will be a drainregion of the low power dissipation semiconductor power device describedin FIG. 1, is formed in the back surface of the N⁺ silicon substrate 1by diffusion or ion implantation, a low power dissipation semiconductorpower device with an excellent performance can be yielded, even if thewidth W of its P⁺ boron implanted region is not uniform in the verticaldirection as shown in FIG. 4A.

In the subsequent annealing process conducted after boron-ionimplantation, boron presents lateral broadening due to diffusion and asa result P⁺ boron implanted regions 3a further approach each other nearthe back surface. However, if the N⁺ drain region and the N⁺ region,which is left as a triangle area in the silicon wafer in FIG. 5, arewell connected, the performance of the low power dissipationsemiconductor power device will not be significantly affected (see theexplanation for FIG. 6D).

Now referring to FIGS. 6A to 6D, a third embodiment of the invention isdescribed, which is a method of forming a super junction by boron andphosphorous implantation using a reversed mask. In FIG. 6A, denoted as1a is a silicon substrate, 2 a boron-ion beam, 3a a P⁺ boron implantedregion, and 4 a shield mask made of a photoresist.

As is the case with the second embodiment of the invention, using ashield mask 4 made of a photoresist, the boron-ion beam 2 is irradiatedonto the silicon substrate 1a, with its acceleration energy beingcontinuously varied, as sown in FIG. 6A. A P⁺ boron implanted region 3ashown by a right-down hatch, is thereby formed inside the siliconsubstrate 1a.

Next, another shield mask 4a made of a photoresist is formed by PEP onthe silicon substrate 1a, of which opening portion and shielding portionare reversed each other of the mask 4, as shown in FIG. 6B. This shieldmask 4a can be formed on the silicon substrate 1a by preparing apositive and negative image photomasks using the same photoresist or byusing positive and negative types of photoresists using the samephotomask.

As a next step, a phosphorous-ion beam 2a is irradiated through theopening portion of the inverted shield mask 4a made of the abovephotoresist, with its acceleration energy being varied continuously, andan N⁺ phosphorous implanted region 3b is formed as shown by a left-downhatch in FIG. 6B. As the ion projection range becomes deeper, the P⁺boron implanted region 3a and the N⁺ phosphorous implanted region 3bbecomes broader. Then toward the back surface, they come to overlap eachother and a compensated region 3c is formed as shown by a crosshatch inFIG. 6B.

By a heat treatment for activation of implanted boron and phosphorous,the boron implanted region 3a and the phosphorous implanted region 3bturn into P⁺ and N⁺, respectively. In the compensated region 3c, wherethe above two regions overlap each other, a P⁺/N⁺ junction plane isformed along the ridge. The boron implanted region becomes a P⁺ regioncompensated by phosphorous and the phosphorous region becomes an N⁺region compensated by boron.

FIG. 6C shows the shape of a super junction formed in the above way. Thecompensated P⁺ region 3a′ and compensated N⁺ region 3b′ after a heattreatment for activation turn into uniform regions of which width andconcentration are constant in the vertical direction.

As a next step, phosphorous is diffused or implanted, and an N⁺ drainregion 5 and an N⁺ source region 6 are formed as shown in FIG. 6D.Further, a gate electrode 7 is formed via a gate insulating film (notshown) so that it may cover the compensated N⁺ region 3b′ connected tothe N⁺ drain region 5 and the compensated P⁺ region 3a′ exposed on thesubstrate surface. Finally, when the source electrode S and the drainelectrode D are formed, the desired low power dissipation semiconductorpower device is completed.

In this way, if the surface of compensated P⁺ region 3a′, which isexposed on the surface of silicon substrate 1a, is inverted to a N-typechannel, the semiconductor device operates as an NMOS-type device. Inother words, the low power dissipation semiconductor power device inFIG. 6D has a small ON resistance because it has a drain junction plane,to which high voltages are applied, made of a super junction consistingof the P⁺ region 3a′ and N⁺ region 3b′ which extend in a directionperpendicular to the wafer surface.

Further, since the drain depletion region extends to N⁺ drain region 5through N⁺ region 3b′ along the super junction, this NMOS-type low powerdissipation semiconductor power device has a large withstand voltage. Itis also obvious that if the above N⁺ regions are replaced by P⁺ regionsa PMOS-type low power dissipation semiconductor power device isobtained.

Now referring to FIG. 7, a forth embodiment of the invention isexplained. The forth embodiment describes a method of forming a superjunction in which a P⁺ silicon ingot is irradiated by a neutron beamthrough a collimator made of lead to transmute silicon atoms intophosphorous atoms by a nuclear reaction.

In FIG. 7, denoted as 10 is a nuclear reactor, 11 a high-speed neutronbeam, 12 a moderator (water) for the high-speed neutron beam, 13 athermal neutron beam after passing through the moderator, 14 a leadcollimator, 15 a collimated neutron beam, and 16 a P⁺ silicon ingot.

By the neutron beam irradiation shown in FIG. 7, a super junctionstructure is formed in which a P⁺ region 17 (part of the P⁺ siliconingot) and an N⁺ region 18 are alternatively piled up. The P⁺ siliconingot 16 is placed as its direction of growth axis becomes parallel withthe neutron beam irradiation direction. The collimated neutron beam 15,which has been collimated via the collimator 14, is irradiated totransmute part of silicon atoms into phosphorous atoms by a nuclearreaction.

The high-speed neutron beam 11 turns into the low energy thermal neutronbeam 13, passing through the moderator 12 (water) to raise the collisioncross section during nuclear reaction.

Stripes of N⁺ regions 18 are formed by the collimated neutron beam 15,which is made by passing the thermal neutron beam 13 through thecollimator 14 where stripes of lead layers are mounted that completelyabsorb neutrons. Then the thickness of each lead layer is determined, sothat neutrons are absorbed sufficiently, the neutron beams becomeparallel to each other in the P⁺ silicon ingot 16, and the widths offormed N⁺ regions 18 become uniform.

Since neutron beams have a high transmission coefficient and a smallbroadening, they are capable of forming N⁺ regions 18 of a uniform widthover the P⁺ silicon ingot 16. If this wafer is sliced in the directionvertical to the irradiation direction (namely, the growth axis ofingot), many silicon substrates each having a super junction formed tothe direction vertical to surface are provided at a time.

Having described the principles of the invention in preferredembodiments, it is appreciated that the invention can be modified inarrangement and detail without departing from such principles. Forexample, although boron has been implanted as a P⁺ impurity in an N⁺silicon substrate in the first and second embodiments of the invention,a silicon substrate is also obtained that has an N⁺ region as superjunction if a silicon substrate having an N⁺ region is employed.

It is obvious that a similar super junction can be formed by implantinga second and first conductivity-type impurities into a first and secondconductivity-type silicon substrates, respectively.

Likewise, in the forth embodiment of the invention, if the P⁺ siliconingot is replaced by a silicon ingot having a P⁺ region, a silicon ingotis obtained that has the P⁺ region as a super junction.

Although the direction of neutron beam irradiation has been parallel tothe growth axis of the silicon ingot, a super junction can be formed inany silicon ingot having a P⁺ region by irradiating a collimated neutronbeam from any direction.

In the forth embodiment of the invention, a neutron beam has beenirradiated onto a P⁺ silicon ingot. However, the ingot is notnecessarily made of silicon. The present invention allows the use ofsemiconductor ingots made of group IV elements such as germanium andsilicon carbide. The present invention can be modified in arrangementand detail without departing from its principles.

As described above, by the method of forming a super junction accordingto the present invention, which does not use conventional complexprocesses like the epitaxial growth but use only efficient processessuch as ion implantation and neutron beam irradiation, a super junctioncan be formed that has an arbitrary and uniform cross-section in thevertical direction. Specifically, the ion implantation and the neutronbeam irradiation have the following advantages:

(1) Since a selective irradiation can be performed by an electric ormagnetic sweep or movement of silicon substrate, the width ofirradiation pattern can be continuously controlled according to changesin ion acceleration energy, and the vertical distribution of implantedions shows an excellent uniformity.

(2) A second conductivity-type region is formed by changing only theacceleration energy after a first conductivity-type region is formed ona silicon substrate using a shield mask made of a photoresist havingstripes of openings with a predetermined aperture width. Then althoughthe vertical distribution of ions becomes relatively less uniform, asuper junction can be formed using only the common ion implantationequipment and PEP without conducting ion beam sweep.

(3) If a first and second conductivity-type regions are formed by ionirradiation onto an intrinsic silicon substrate by the use of a shieldmask made of a photoresist with striped shape openings of a specificwidth and another shield mask made of a photoresist in the reversedrelation to the above photoresist, a uniform super junction is formed inthe vertical direction because the lateral broadenings of ionscompensate each other due to scattering.

(4) If a collimated neutron beam is irradiated onto a P⁺ silicon ingot,a uniform super junction is formed there, because the transmissioncoefficient of neutron beam is high enough to precisely transmute theirradiated region into an N⁺ region with less broadening. If the neutronbeam is irradiated in parallel with the growth axis of the silicon ingotand silicon wafers are sliced out in the direction vertical to thegrowth axis as is the case with common silicon wafers, many siliconsubstrates each having a precision super junction over its surface canbe produced at a time.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. A semiconductor device manufacturing method of forming a secondconductivity-type region by irradiating impurity ions onto a firstconductivity-type semiconductor substrate; wherein the irradiatingimpurity ions is performed to form a junction structure comprising avertical junction group where a first conductivity-type region and thesecond conductivity-type region are alternatively arranged vertically toa surface of the semiconductor substrate; and wherein the impurity ionirradiated region is restricted by a shield mask intercepting saidimpurity ions and the impurity ion acceleration energy is controlled toprovide a uniform impurity distribution in the direction of irradiationin said second conductivity-type region.
 2. A semiconductor devicemanufacturing method of forming at least one of a first and secondconductivity-type regions in a semiconductor substrate by selectivelyirradiating impurity ions onto said semiconductor substrate; wherein theselectively irradiating impurity ions is performed to form a junctionstructure comprising a vertical junction group where the firstconductivity-type region and the second conductivity-type region arealternatively arranged vertically to a surface of the semiconductorsubstrate; and wherein the impurity distributions in said first andsecond conductivity-type regions are uniform in the direction ofirradiation, and the impurity ion acceleration energy and the area ofeach region irradiated by said impurity ions are controlled so that thecross-sectional shape and cross-section area of said first and secondconductivity-type regions on planes perpendicular to the direction ofirradiation may be are uniform in the direction of irradiation.
 3. Thesemiconductor device manufacturing method according to claim 2, whereinthe control of the area of said irradiated region comprises the steps offorming an ion beam made of impurity ions and sweeping the ion beam inthe vertical and horizontal directions on the irradiated region, and theacceleration energy and the area of the irradiated region are controlledby changing the area of said irradiated region according to changes insaid acceleration energy.
 4. The semiconductor device manufacturingmethod according to claim 3, wherein said impurity ion beam iselectrically swept on the irradiated region.
 5. The semiconductor devicemanufacturing method according to claim 3, wherein said impurity ionbeam is magnetically swept on the irradiated region.
 6. Thesemiconductor device manufacturing method according to claim 3, whereinsaid impurity ion beam is swept on the irradiated region by moving thesemiconductor substrate.
 7. The semiconductor device manufacturingmethod according to claim 3, wherein the acceleration energy and thearea of the irradiated region are controlled by decreasing the area ofthe irradiated region according to increase in the acceleration energy.8. The semiconductor device manufacturing method according to claim 3,wherein the acceleration energy and the area of the irradiated regionare controlled by increasing the area of the irradiated region accordingto decrease in the acceleration energy.
 9. The semiconductor devicemanufacturing method according to claim 2, wherein the area of theirradiated region is restricted by a shield mask intercepting saidimpurity ions, and the acceleration energy and the area of theirradiated region are controlled by changing the area of each opening ofsaid shield mask intercepting impurity ions according to changes in theacceleration energy.
 10. The semiconductor device manufacturing methodaccording to claim 9, wherein the acceleration energy and the area ofthe irradiated region are controlled by decreasing the area of eachopening of said shield mask intercepting impurity ions according toincrease in the acceleration energy.
 11. The semiconductor devicemanufacturing method according to claim 9, wherein the accelerationenergy and the area of the irradiated region are controlled byincreasing the area of each opening of said shield mask interceptingimpurity ions according to decrease in the acceleration energy.
 12. Thesemiconductor device manufacturing method of forming a firstconductivity-type region and a second conductivity-type region on asemiconductor substrate by irradiating impurity ions onto saidsemiconductor substrate; wherein the irradiating impurity ions isperformed to form a junction structure comprising a vertical junctiongroup where the first conductivity-type region and the secondconductivity-type region are alternatively arranged vertically to asurface of the semiconductor substrate; and wherein the regionsirradiated by impurity ions are restricted by impurity ion interceptingshield masks which are in an inverted imaging relation to each other sothat the cross-sectional shape and the cross-section area of the firstand second conductivity-type regions on planes perpendicular to thedirection of irradiation may be are uniform along the direction ofirradiation, and the impurity ion acceleration energy is controlled tomake the impurity ion distributions in the first and secondconductivity-type regions uniform along the direction of irradiation.13. The semiconductor device manufacturing method according to claim 12,wherein said impurity ion intercepting shield masks which are in aninverted imaging relation to each other are formed by printing the samemask patterns on the semiconductor substrate by the use of a positiveresist and a negative resist.
 14. A semiconductor device manufacturingmethod of forming an N⁺ region by irradiating a neutron beam onto asemiconductor ingot having a P⁺ region; wherein the incident directionof said neutron beam is collimated to make the cross-sectional shape andthe cross-section area of said N⁺ region on planes perpendicular to thedirection of irradiation uniform along the direction of irradiation, andthe impurity distribution in said N⁺ region is controlled to be uniformalong the direction of irradiation.
 15. The semiconductor devicemanufacturing method according to claim 14, wherein the semiconductorhaving the P⁺ region is an P⁺ type semiconductor ingot and the incidentdirection of said neutron beam is parallel to the growth axis of said P⁺type semiconductor ingot.
 16. The semiconductor device manufacturingmethod according to claim 14, wherein said semiconductor ingot is madeof silicon.
 17. The semiconductor device manufacturing method accordingto claim 14, wherein said semiconductor ingot is made of germanium. 18.The semiconductor device manufacturing method according to claim 14,wherein said semiconductor ingot is made of silicon carbide.
 19. Thesemiconductor device manufacturing method according to claim 1, whereinthe first conductivity-type region includes plural portions, the secondconductivity-type region includes plural portions, and the pluralportions of the first conductivity-type region are alternativelyarranged with the plural portions of the second conductivity-type regionand vertically to the surface of the semiconductor substrate.
 20. Thesemiconductor device manufacturing method according to claim 2, whereinthe first conductivity-type region includes plural portions, the secondconductivity-type region includes plural portions, and the pluralportions of the first conductivity-type region are alternativelyarranged with the plural portions of the second conductivity-type regionand vertically to the surface of the semiconductor substrate.
 21. Thesemiconductor device manufacturing method according to claim 12, whereinthe first conductivity-type region includes plural portions, the secondconductivity-type region includes plural portions, and the pluralportions of the first conductivity-type region are alternativelyarranged with the plural portions of the second conductivity-type regionand vertically to the surface of the semiconductor substrate.